1. Technical Field
The present disclosure relates to wireless communication systems, and more particularly to a mobile communication device that includes a voltage controlled oscillator.
2. Background Information
Wireless communication devices originally provided only the capability of voice communication. Now wireless communication devices have evolved to provide other communication, information and entertainment capabilities communicated over a broader range of frequencies. These additional capabilities require frequency synthesizers operable over increasingly broad, tunable frequency ranges with low noise sensitivity. Achieving low noise sensitivity is particularly difficult where the added function requires a broad, tunable frequency range for operation. For example, receiving frequency modulation (FM) radio signals is one communication function that requires a frequency synthesizer to generate signals over a broad range of frequencies to process the radio signals received over the entire FM frequency band. For a mobile communication device that is to be sold in a worldwide market, it is desirable to receive radio signals not only in the FM band used in the United States, Canada and Europe (87.5 MHz to 108.0 MHz), but also in the FM band used in Japan (76 MHz to 90 MHz). Thus, the overall frequency range of radio signals to be processed is from 76.0 MHz to 108.0 MHz.
A typical frequency synthesizer used in Radio Frequency (RF) processing of voice and data communications employs a Phase Locked Loop (PLL) where the PLL includes a voltage-controlled oscillator (VCO) with an inductor-capacitor (LC) tank. It would be undesirable to use a frequency synthesizer with a VCO that oscillates over the relatively low frequencies between 76 and 108 MHz. Such a VCO would be large and could not be practically integrated onto a single integrated circuit with the FM transceiver. Thus, frequency synthesizers for communication functions typically generate higher frequency signals that are divided down by a divisor. But, the absolute range of the higher frequency signals increases proportionately to the divisor. For example, a VCO tunable from 2.736 to 3.127 GHz, useable to address a range of FM radio signals, requires a tunable frequency range of 391 MHz.
A large VCO gain is typically required to realize a relatively broad frequency tuning range. However, a large VCO gain tends to increase the noise sensitivity of the PLL and increases the loop sensitivity to power supply noise. Also, for a given loop bandwidth, a large VCO gain requires a relatively large loop filter capacitor, complicating on-chip integration. Thus, a design for a VCO is desired that meets the requirements of a wide frequency tuning range and minimizes the noise sensitivity of the PLL by maintaining a relatively low VCO gain.
FIG. 1 (prior art) illustrates a typical VCO design with a digitally controlled capacitor bank. VCO 11 uses a voltage controlled capacitor (varactor) 15 to actively control the oscillation frequency of the VCO output signal 17. By varying the capacitance of the varactor 15 in response to a control voltage 16 the overall capacitance of LC resonant tank 12 and the resulting VCO oscillation frequency are changed. To keep the VCO gain relatively low, the range of capacitance of varactor 15 is minimized. However, this limits the range of oscillation frequencies achievable by control of varactor 15 alone. To compensate, a digitally controlled capacitor bank 13 is coupled in parallel with the varactor to provide a digitally controlled capacitance value upon which the capacitance value of the varactor 15 is added. The digitally controlled capacitor bank 13 includes tuning capacitor elements coupled in parallel as illustrated. Each tuning capacitor element includes a pair of capacitors and a switching element. Digital control lines 14 control the capacitance value of the digitally controlled capacitor bank 13 by selectively activating each tuning capacitor element. Thus, the range of tunable frequencies of VCO 11 is expanded.
A successful capacitor bank design requires that each possible target frequency (and corresponding capacitance) within the tunable frequency range be addressable by some combination of tuning capacitor elements within the capacitor bank 13 and the varactor 15. Each incremental step of capacitance of the capacitor bank 13 should not leave gaps in the corresponding range of capacitance that cannot be compensated by the varactor 15. Each incremental step should be small and uniform to limit the size of varactor 15. In modern designs, a capacitor bank of 10-bit resolution is often required to meet design requirements.
When each tuning capacitor element is designed to provide the same capacitance, the resulting capacitor bank is commonly termed a thermometer-coded capacitor bank. A relatively linear, step-wise increase in capacitance results as each successive tuning capacitor element is activated. But, a single segment thermometer-coded implementation requires a relatively large number of capacitors to achieve high resolution. For example, a 10-bit solution would require 1023 (2n-1) individual capacitors. The complexity and size of the physical routing and decoder logic required to provide and control such a large number of capacitors is prohibitive. This limits the practicability of a single segment, thermometer-coded capacitor bank.
To reduce the number of capacitors required to address a range of tunable frequencies, a binary coded approach may be employed. In an exemplary 4-bit binary coded approach, a first tuning capacitor element has a first capacitance value, a second tuning capacitor element has twice the capacitance, a third tuning capacitor element has four times the capacitance, and a fourth tuning capacitor element has 16 times the capacitance. The binary coded approach provides a broad range of capacitance with relatively few capacitors. For example, a 10-bit solution requires only ten tuning capacitor elements. However, the binary coded method is susceptible to capacitor mismatches. In practice, individual capacitor values vary from their nominal value and these mismatches result in irregular steps in capacitance for each increment of the capacitor bank code.
FIG. 2 (prior art) illustrates an example of the change of capacitance for each increment of the capacitor bank code of a 7-bit binary coded design. Under ideal conditions, the incremental change of capacitance should be a single value for each step in the code. However, in practice, as illustrated in FIG. 2, a binary coded implementation exhibits a broad variation in incremental change of capacitance. To address each possible target frequency in a range of tunable frequencies, a varactor 15 with a relatively large tunable capacitance is required. This results in an undesireably large VCO gain.
One approach to minimize this limitation of a binary coded implementation is to introduce a two-segment capacitor bank where one segment is binary coded and the second segment is thermometer-coded. Such a two-segment approach has the potential to reduce the number of tuning capacitor elements required to achieve a particular value of capacitor bank resolution. For additional detail, see: U.S. Pat. No. 7,113,052, entitled “Coarse Frequency Tuning In A Voltage Controlled Oscillator”, issued Sep. 26, 2006, by Jeremy D. Dunworth.
Another approach to reduce variation in the incremental change of capacitance is to trim the capacitors of the capacitor bank at the manufacturing stage to minimize mismatches. However, this approach is costly and adds complexity to the manufacturing process. Another approach is to calibrate the code associated with each individual capacitor bank to match the target frequency for each step. Such a calibrated code may be stored in an on-board look-up table for future use. Again, this approach is costly and adds complexity to the control logic implementation. Thus, a digitally controlled tuning capacitor bank of relatively few tuning capacitor elements is desired that is capable of providing a broad range of capacitance values; addressable in uniform steps at high resolution.